This invention relates generally to a semiconductor integrated circuit device, and more particularly to a technique which is effective when applied to a semiconductor integrated circuit device equipped with a read-only memory function and capable of electrically programming data and of erasing the data.
One of the most important technical problems to be solved for EPROM is an example of semiconductor devices using field effect transistors having a floating gate as memory cells is to shorten write-in time by improving writing efficiency and to shorten readout time by improving reading efficiency.
Writing efficiency can be improved by intensifying the electric field close to the drain region of a memory cell and increasing the injection quantity of hot carriers into the floating gate.
Reading efficiency can be improved by reducing the channel resistance of the memory cell and increasing the intensity of current flowing through the source and drain regions.
The electric field near the drain region can be intensified and the channel resistance can be reduced by, for example, converting the memory cell, that is, the field effect transistor, to a short channel type.
However, when a highly integrated EPROM having a channel length of below about 1.5 .mu.m is fabricated, a phenomenon occurs in which the threshold voltage of the memory cell fluctuates considerably due to the short channel effect.
Therefore, the inventor of the present invention has attempted to apply a lightly doped drain (LDD) structure to the EPROM memory cell. For details of the LDD structure, refer, for example to "IEEE Transactions on Electron Devices", Vol. ED-29, No. 4, April, 1982, pp 590-596.
As a result of experiments and examination regarding this this technique, however, the inventor of the present invention has found the following problems when an LDD structure is applied to a field effect transistor which is an EPROM memory cell:
(1) A region, which is formed between a region to be formed as a channel of the field effect transistor in which the memory cell and a virtual drain region having a high impurity concentration, is formed with a low impurity concentration such as about 1.times.10.sup.13 atoms/cm.sup.2. Therefore, the p-n junction formed by a semiconductor substrate and the low impurity concentration region is one that is formed mutually by a p-n junction between the low impurity concentration regions. This in turn reduces field intensity near the drain region; hence, writing efficiency drops.
(2) The low impurity concentration region has a high resistance of about 1 .OMEGA..quadrature. which is about 20 to 30 times higher than the resistance of the virtual drain region. Therefore, the intensity of the current that flows between the source and drain regions of the field effect transistor decreases; hence, the reading efficiency falls off.
(3) Because of the problems described in the items (1) and (2) above, the size of the memory cell cannot be reduced by converting the field effect transistor of the memory cell to the short channel type, so that the integration density of the EPROM cannot be improved.
(4) Because of the problems (1) through (3), high-density integration, high writing efficiency and high reading efficiency for the EPROM cannot be accomplished.